1. Field of Invention
The present invention relates to a method for fabricating semiconductor memory device. More particularly, the present invention relates to a method for fabricating a non-volatile memory device.
2. Description of Related Art
In several types of non-volatile memory device, the EEPROM device, having the advantages of multiple times of operations for write, read and erase, and stored data being not lost after power off, has been a necessary memory device widely used in personal computer and other electronic equipment. The typical EEPROM device uses the doped polysilicon as the floating gate and control gate. The control gate is directly disposed above the floating gate, and a dielectric layer is disposed between the floating gate and the control gate. The floating gate is separated from the substrate by a tunneling oxide. A positive voltage or a negative voltage is applied on the control gate to control the electrons to be injected or discharged from the floating gate, so as to achieve the memory function. However, when the tunnel oxide layer under the polysilicon floating gate layer has defects, it easily causes the current leakage of the device, and affects the device reliability.
Therefore, in order to solve the issue of current leakage in EEPROM device, the conventional method uses the charge trapping layer to replace the conventional polysilicon floating gate in the conventional memory device. Material for the charge trapping layer can be silicon nitride. For this charge trapping layer by silicon nitride, an oxide layer is formed on each up and lower side, so as to form a stacked structure of silicon-oxide/silicon-nitride/silicon-oxide (ONO). The ROM device with the stacked structure for the gate electrode can be referred to silicon-oxide-nitride-oxide-silicon (SONOS) memory device.
In the other hand, during the processes for fabricating the memory device, the fabrication processes for the memory cell region and the periphery circuit region are usually integrated together. However, due to difference of requirements on the fabrication processes for the memory cell region and the periphery circuit region, when the memory cell region (or periphery circuit region) is in fabrication, a mask is needed to mask the periphery circuit region (or memory cell region). This causes the complexity for fabrication process and increase of fabrication cost.
Also and, in the conventional method for fabrication the memory device, the memory cells have a single characteristic. How to simultaneously fabricate the memory cells with multiple characteristics under the processes is the main concerning in development.